Logic cores are becoming increasingly popular in the design of integrated circuits. Whereas in the past, integrated circuits were largely designed from scratch, today's integrated circuits are designed using pre-designed logic elements that are made available in logic cores. One reason for the popularity of logic cores is the trend toward standards-based implementations. Additional reasons includes desires to speed the design process and reduce costs.
Parameterized logic cores permit a designer to partially customize predefined logic circuits. For example, a synchronous FIFO element of a logic core may include port-width and depth parameters which allow the designer to tailor the logic to satisfy application-specific requirements.
Designers who use logic cores rely on the fact that the elements operate correctly, both individually and when connected to other logic elements. Thus, logic core vendors must sufficiently test the logic, not only to verify that the circuit performs the specified function for commonly used parameters, but also to verify that circuit operates satisfactorily for infrequently used parameters.
While testing individual elements of a logic core using various permutations of the available parameters may be feasible, the number of permutations of parameters when considering various combinations of the logic elements in the core quickly escalates. Thus, there may be more permutations or parameters for a logic core than can feasibly be tested.
Testers often resort to constructing test sets that reflect a representative set of possible parameter permutations. While this approach can be tailored to fit the time available for testing, the associated risk is that some errors may go undetected. To increase test coverage more resources must be devoted to testing.
A method that address the aforementioned problems, as well as other related problems, is therefore desirable.